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Quad Pin Timing Formatter ADATE207
FEATURES
4-channel timing formatter 256 waveforms per channel 4 independent event edges per waveform STIL IEEE 1450-1999-compatible events 4-period range for each edge 39.06 ps timing resolution 2.5 ns minimum edge refire rate All drive formats supported 100 MHz base vector rate x2 and x4 high speed modes x2 pin multiplexing 1 ns minimum pulse width 32-bit fail counter per channel 4-bit pin capture per channel Air cooled, low power CMOS design 6 W at 100 MHz base rate 2.5 V power supply Differential DCL interface control TMU multiplexer
FUNCTIONAL BLOCK DIAGRAM
ADATE207
PATTERN TIME SET MEMORY QUAD EDGE GENERATOR FAIL DETECTION FORMAT COMPARE LOGIC DCL INTERFACE
FAIL
PATTERN
TIME SET MEMORY
QUAD EDGE GENERATOR FAIL DETECTION
FAIL
FORMAT COMPARE LOGIC
DCL INTERFACE
PATTERN
TIME SET MEMORY
QUAD EDGE GENERATOR FAIL DETECTION
FAIL
FORMAT COMPARE LOGIC
DCL INTERFACE
PATTERN
TIME SET MEMORY
QUAD EDGE GENERATOR FAIL DETECTION
Automatic test equipment (ATE) High speed digital instrumentation Pulse generation
Figure 1.
GENERAL DESCRIPTION
The ADATE207 is a timing generator and formatter for automatic test equipment (ATE) equipment. The ADATE207 provides four independent channels with a 100 MHz base vector rate of timing and formatting for ATE digital pins. It interfaces between the pattern memory,and the driver, comparator, and load (DCL) chips for complete digital pins. The ADATE207 accepts up to eight bits of pattern data per pin and can produce formatted outputs and perform comparisons of DUT expected responses. Each channel of the ADATE207 provides 256 selectable waveforms, wherein each waveform consists of up to four possible events. Each event consists of a programmable timing edge and a STIL-compatible (IEEE Standard 1450-1999) set. Each timing edge generator can produce an edge with a span of four periods with a 39.06 ps edge placement resolution. The delay
generators use a reference master clock of 100 MHz and provide programmable delays based upon counts of the clock and a compensated CMOS analog timing vernier. The programmable delay generators can be additionally delayed by a global 8-bit input value that is shared across all edges. The format and compare logic support x2 pin multiplexing to allow the trading of pin count for speed. Each channel provides a 4-bit DUT output capture supporting mixed signal receive memory applications. The fail detection logic includes a 32-bit fail accumulation register per channel. An external TMU is supported with three 8-to-1 multiplexers. This allows the dual comparator outputs of any pin to be multiplexed to any of the three outputs: arm, start, or stop signals.
Rev. 0
Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 www.analog.com Fax: 781.461.3113 (c)2007 Analog Devices, Inc. All rights reserved.
05557-001
APPLICATIONS
FAIL
FORMAT COMPARE LOGIC
DCL INTERFACE
ADATE207 TABLE OF CONTENTS
Features .............................................................................................. 1 Applications....................................................................................... 1 Functional Block Diagram .............................................................. 1 General Description ......................................................................... 1 Specifications..................................................................................... 3 DC Specifications ......................................................................... 3 AC Specifications.......................................................................... 4 Timing Diagrams.......................................................................... 5 Absolute Maximum Ratings............................................................ 6 Thermal Resistance ...................................................................... 6 Bypassing Scheme ........................................................................ 6 ESD Caution.................................................................................. 6 Pin Configurations and Function Descriptions ........................... 7 Theory of Operation ...................................................................... 12 Waveform Memory .................................................................... 12 Event Generators ........................................................................ 12 Delay Generation........................................................................ 12 Vernier Resolution ..................................................................... 12 Drive and Compare Logic......................................................... 13 Pipeline Considerations............................................................. 14 DUT Capture .............................................................................. 15 TMU Multiplexer ....................................................................... 15 Low Jitter Clock Driver ............................................................. 15 Clock Generator Mode .............................................................. 15 Device Reset................................................................................ 15 Temperature Diode .................................................................... 17 High Speed Differential DCL Interface................................... 17 Control and Status Register Interface .......................................... 18 Read/Write Function ................................................................. 18 Control and Status Registers ......................................................... 21 Channel Specific and Common Registers .............................. 22 Chip-Specific (Common) Registers......................................... 30 Application Information ............................................................... 34 Time Measurement Support ..................................................... 34 Outline Dimensions ....................................................................... 35 Ordering Guide .......................................................................... 35
REVISION HISTORY
5/07--Revision 0: Initial Version
Rev. 0 | Page 2 of 36
ADATE207 SPECIFICATIONS
DC SPECIFICATIONS
TC = 85C 5C, VDD = 2.5 V, unless otherwise noted. Table 1.
Parameter POWER SUPPLY Operating Supply Current, IDD Power Dissipation 1 Conditions All channels repeating pattern of 1/H/0/L across D0/D1/D2/D3 edges every 20 ns All channels repeating pattern of 1/H/0/L across D0/D1/D2/D3 edges every 20 ns All channels repeating pattern of H/L/H/L across D0/D1/D2/D3 edges every 10 ns Idle mode; no patterns bursting All channels repeating pattern of 1/0/1/0 across D0/D1/D2/D3 edges every 10 ns Idle mode; no patterns bursting Min Typ 2.5 6.3 6.85 5.7 2.7 2.2 Max 2.7 7.1 Unit A W W W A A
Operating Supply Current, IDD
DIGITAL INPUTS LVCMOS25 VIL IIL VIH IIH Pin Capacitance Differential Inputs with Internal Termination VDIFF Input Voltage Range Differential inputs with External Termination VDIFF Input Voltage Range R Termination DIGITAL BIDIRECTIONALS LVCMOS25 VIL IIL VIH IIH DIGITAL OUTPUTS LVCMOS25 VOL VOH Open Drain Differential Outputs VDIFF VOL (Individual Leg of Pair) VOH (Individual Leg of Pair) Ambient Potential Operating Potential Temperature Coefficient
1
VIL = 0 V 1.7 VIH = 2.5 V Guaranteed by simulation
0.7 1 1 3.5
V A V A pF
200 1.0
VDD
mV V
200 1.0 50 15%
VDD
mV V
VIL = 0 V 1.7 VIH = 2.5 V
0.7 1 1
V A V A
IOL = 8 mA IOH = 8 mA REF_1K > 100 k to GND VTERM = 50 to VDD VTERM = 50 to VDD VTERM = 50 to VDD IDIODE = 100 A IDIODE = 100 A IDIODE = 100 A
0.4 VDD - 0.4 200 2.2 715 600 1.4 630 300 2.49
V V mV V V mV mV mV/C
Power dissipation specifically indicates part dissipation and does not include power dissipated in external terminations.
Rev. 0 | Page 3 of 36
ADATE207
AC SPECIFICATIONS
TC = 85C 5C, VDD = 2.5 V, unless otherwise noted. Table 2.
Parameter CLOCK INPUTS Master Clock (MCLK) Frequency MCLK Duty Cycle DRIVE OUTPUTS Output Pulse Width COMPARE INPUTS Minimum Comparison Window Width Minimum Detectable Glitch Width EDGE PERFORMANCE Retrigger Time Edge Delay Vernier Resolution Vernier Timing DNL Vernier Timing INL Vernier Temperature Coefficient Edge Jitter CONTROL AND STATUS REGISTER (CSR) INTERFACE Clock Period Setup Time (tBSU) Hold Time (tBH) Clock to Output (tBCO) Clock to Tristate (tBCZ) Clock to Data Valid from Tristate (tBCZV) DIGITAL INPUTS Set Up (tISU) Hold Time (tIH) DIGITAL OUTPUTS Clock to Output (tOCO) JTAG PORTS JTAG Clock Period Setup Time (tSSU) Hold Time (tSH) Clock to Output (tSCO) Conditions Min Typ 100 50 Max Unit MHz % ns 1.25 1.25 2.5 0 39.06 -150 -150 MCLK jitter 5 ps rms 4 20 10 MCLK MCLK MCLK 1.1 0.5 2.5 2.3 0 1.7 0.5 0.7 100 50 50 50 1.6 +150 +150 ns ns ns Lesser of 4 T0 cycles or 163.8 s ps ps ps ps/C ps rms ns ns ns ns ns ns ns ns ns ns ns ns ns
46 Timing error < 125 ps 1
54
7.0 4.2 7.0
MCLK MCLK MCLK
JTAG CLOCK JTAG CLOCK JTAG CLOCK
Rev. 0 | Page 4 of 36
ADATE207
TIMING DIAGRAMS
MCLK_P MCLK_N
DIGITAL INPUTS
tISU
tIH
DIGITAL OUTPUTS
tOCO(MIN) tOCO(MAX)
05557-007
Figure 2. Timing Diagram for Inputs and Outputs
JTAG
JTAG INPUT
tJSU
tJH
JTAG OUTPUT
tJCO
Figure 3. Timing Diagram for Scan Inputs and Scan Outputs
MCLK_P MCLK_N
BIDIRECTIONAL (WRITES)
tBSU
tBH
tBCZV
BIDIRECTIONAL (READS)
tBCO(MIN) tBCO(MAX) tBCZ
05557-008
Figure 4. Timing Diagram for Bidirectional Reads and Writes
Rev. 0 | Page 5 of 36
05557-015
ADATE207 ABSOLUTE MAXIMUM RATINGS
Table 3.
Parameter VDD Digital Inputs Resistor Termination pins Resistor Termination Current Termination Pad Current Junction Temperature Storage Temperature Rating -0.3 V to +2.8 V -0.3 V to VDD + 0.3 V -0.3 to VDD + 0.3 V 12 mA max 12 mA max 125C -40 to 125C
BYPASSING SCHEME
For decoupling, best practice suggests that to preserve as much of the plane-to-plane capacitance as possible, do not perforate the planes for VSS and VDD. Secondly, it is advisable to decouple VDD to VSS by using 0.1 F high frequency ceramic capacitors. The trace to the capacitor should be kept to an absolute minimum length. It is recommend that one capacitor be placed in the corner of the chip and one in the middle of each side for a total of eight capacitors for VDD to VSS. Furthermore, decouple IOVDD to IOVSS on each side of the device. It is recommended that 10 F tantalum or ceramic capacitors be used for low frequency decoupling around the device. It is not important for these capacitors to be close to the device. Table 6. Data Table for 256-Lead Ball Grid Array, Thermally Enhanced, 27 mm x 27 mm Body
Dimension A A1 A2 D D1 E E1 b e aaa bbb ccc ddd eee fff S Minimum (mm) 0.50 0.60 26.90 24.03 26.90 24.03 0.60 Nominal (mm) 0.60 0.80 27.00 24.13 27.00 24.13 0.75 1.27 0.20 0.25 0.35 0.20 0.30 0.15 0.635 Maximum (mm) 1.70 0.70 1.00 27.10 24.23 27.10 24.23 0.90
Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Table 4. Recommended Operating/Environmental Conditions
Parameter VDD Case Temperature (TC) Relative Humidity (Noncondensing) Min 2.375 Typ 2.5 85 Max 2.625 85 Unit V C %
THERMAL RESISTANCE
Table 5. Thermal Resistance
Package Type 256-Lead BGA_ED In Still Air 200 LFPM 400 LFPM JA 14.3 12.0 11.2 JC 1.5 Unit C/W C/W C/W C/W
ESD CAUTION
Rev. 0 | Page 6 of 36
ADATE207 PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS
20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 A B
PATTERN DATA PERIOD DATA
CH0 DCL I/F
C D E
CH1 DCL I/F
F G H
ADATE207
COMPARE FAILS RECEIVE DATA CH2 DCL I/F
ADATE207
CH3 DCL I/F
BOTTOM VIEW (Not to Scale)
05557-009
J K L M N P R T U V Y
05557-014
COMMAND/ STATUS BUS
TIME MEASUREMENT
W
Figure 5. Connection Overview Diagram
Figure 6. Ball Grid Array
Table 7. Pin Function Descriptions
Pin No. B4, A4, C5, D6 Mnemonic PAT_MASK[3:0] Input/Output 1 I Type LVCMOS25 Description Mask Failures. Used to mask failures on D3, D2, D1 and D0 edges, respectively. Clocked by MCLK. Channel 0 Waveform Memory Address. Use these pins to address waveform memory for Channel 0. Clocked by MCLK. Channel 1 Waveform Memory Address. Use these pins to address waveform memory for Channel 1. Clocked by MCLK. Channel 2 Waveform Memory Address. Use these pins to address waveform memory for Channel 2. Clocked by MCLK. Channel 3 Waveform Memory Address. Use these pins to address waveform memory for Channel 3. Clocked by MCLK. Fails on D3, D2, D1 and D0 Edges for Channel 0. Clocked by MCLK. Fails on D3, D2, D1 and D0 Edges for Channel 1. Clocked by MCLK. Fails on D3, D2, D1 and D0 Edges for Channel 2. Clocked by MCLK. Fails on D3, D2, D1 and D0 Edges for Channel 3. Clocked by MCLK. DUT Capture Data from Channel 0. Clocked by MCLK. DUT Capture Data from Channel 1. Clocked by MCLK. DUT Capture Data from Channel 2. Clocked by MCLK. DUT Capture Data from Channel 3. Clocked by MCLK.
T3, U1, U2, T4, U3, V4, U5, W4
PAT_PATDATA_0[7:0]
I
LVCMOS25
B5, A5, C6, B6, A6, C7, B7, D8
PAT_PATDATA_1[7:0]
I
LVCMOS25
W212, V12, Y13, U12, W13, V13, Y14, W14 A16, B16, D15, C16, A17, B17, D16, C17 Y4, W5, V6 B8, A8, B9, B10 V8, W8, W9, Y9 B12, C12, B13, A14 W6, Y6, W7, Y7 C10, A11, B11, A12 V10, W10, Y10, W11 B14, C14, A15, B15
PAT_PATDATA_2[7:0]
I
LVCMOS25
PAT_PATDATA_3[7:0]
I
LVCMOS25
PAT_FAIL_0[3:0] PAT_FAIL_1[3:0] PAT_FAIL_2[3:0] PAT_FAIL_3[3:0] PAT_DUTDATA_0[3:0] PAT_DUTDATA_1[3:0] PAT_DUTDATA_2[3:0] PAT_DUTDATA_3[3:0]
O O O O O O O O
LVCMOS25 LVCMOS25 LVCMOS25 LVCMOS25 LVCMOS25 LVCMOS25 LVCMOS25 LVCMOS25
Rev. 0 | Page 7 of 36
ADATE207
Pin No. D5 Mnemonic PAT_DATA_VALID Input/Output 1 I Type LVCMOS25 Description Indicates Pattern Bursting. When not asserted, edges are disabled and the drive and expect signals are static. Clocked by MCLK. Indicates the Start of a T0 Period. Clocked by MCLK. Indicates the Start of a C0 Period. Clocked by MCLK. Global Delay Input For All Edges. Clocked by MCLK. Differential Tristate Output. Noninverted TMU ARM multiplexer output. High-Z when not enabled. Differential Tristate Output. Inverted TMU ARM multiplexer output. High-Z when not enabled. Differential Tristate Output. Noninverted TMU START multiplexer output. High-Z when not enabled. Differential Tristate Output. Inverted TMU START multiplexer output. High-Z when not enabled. Noninverted TMU STOP Multiplexer Output. Differential tristate output. High-Z when not enabled. Inverted TMU STOP Multiplexer Output. Differential tristate output. High-Z when not enabled. Noninverted DCL Drive Data Signal for Channel 0. Inverted DCL Drive Data Signal for Channel 0. Noninverted DCL Drive Data Signal for Channel 1. Inverted DCL Drive Data Signal for Channel 1. Noninverted DCL Drive Data Signal for Channel 2. Inverted DCL Drive Data Signal for Channel 2. Noninverted DCL Drive Data Signal for Channel 3. Inverted DCL Drive Data Signal for Channel 3. Noninverted DCL Drive Enable Signal for Channel 0. Inverted DCL Drive Enable Signal for Channel 0. Noninverted DCL Drive Enable Signal for Channel 1. Inverted DCL Drive Enable Signal for Channel 1. Noninverted DCL Drive Enable Signal for Channel 2. Inverted DCL Drive Enable Signal for Channel 2. Noninverted DCL Drive Enable Signal for Channel 3.
F3 E1 C4, D3, E4, D2, D1, E3, F4, E2 F18
PER_EARLY_T0EN PER_EARLY_C0EN INPUT_DELAY[7:0] TMU_ARM_P
I I I D, O
LVCMOS25 LVCMOS25 LVCMOS25 Differential open-drain Differential open-drain Differential open-drain Differential open-drain Differential open-drain Differential open-drain Differential open-drain Differential open-drain Differential open-drain Differential open-drain Differential open-drain Differential open-drain Differential open-drain Differential open-drain Differential open-drain Differential open-drain Differential open-drain Differential open-drain Differential open-drain Differential open-drain Differential open-drain
E20
TMU_ARM_N
D, O
E19
TMU_START_P
D, O
F17
TMU_START_N
D, O
E18
TMU_STOP_P
D, O
D20
TMU_STOP_N
D, O
P2 P1 G3 H4 P19 P20 G18 H17 N3 N2 G2 G1 N18 N19 G19
DR_DATA_CH0_P DR_DATA_CH0_N DR_DATA_CH1_P DR_DATA_CH1_N DR_DATA_CH2_P DR_DATA_CH2_N DR_DATA_CH3_P DR_DATA_CH3_N DR_EN_CH0_P DR_EN_CH0_N DR_EN_CH1_P DR_EN_CH1_N DR_EN_CH2_P DR_EN_CH2_N DR_EN_CH3_P
D, O D, O D, O D, O D, O DO D, O D, O D, O D, O D, O D, O D, O D, O D, O
Rev. 0 | Page 8 of 36
ADATE207
Pin No. G20 L20 Mnemonic DR_EN_CH3_N LJ_CLK_P Input/Output 1 D, O D, I Type Differential open-drain Differential input Differential Input Differential input terminated Differential input terminated Differential input terminated Differential input terminated Differential input terminated Differential input terminated Differential input terminated Differential input terminated Differential input terminated Differential input terminated Differential input terminated Differential input terminated Differential input terminated Differential Input terminated Differential input terminated Differential input terminated Analog Description Inverted DCL Drive Enable Signal for Channel 3. Noninverted Low Jitter Clock Input. This pin can be multiplexed onto DR_DATA outputs for Channel 2 and Channel 3. Inverted Low Jitter Clock Input. This pin can be multiplexed onto DR_DATA outputs for Channel 2 and Channel 3. Noninverted DCL High Comparator Signal for Channel 0. Differential signal is Logic 1 when the DUT output is higher than VOH. Inverted DCL High Comparator Signal for Channel 0. Noninverted DCL High Comparator Signal for Channel 1. Differential signal is Logic 1 when the DUT output is higher than VOH. Inverted DCL High Comparator Signal for Channel 1. Noninverted DCL High Comparator Signal for Channel 2. Differential signal is Logic 1 when the DUT output is higher than VOH. Inverted DCL High Comparator Signal for Channel 2. Noninverted DCL High Comparator Signal for Channel 3. Differential signal is Logic 1 when the DUT output is higher than VOH. Inverted DCL High Comparator Signal for Channel 3. Noninverted DCL Low Comparator Signal for Channel 0. Differential signal is Logic 1 when the DUT output is higher than VOL. Inverted Low Comparator Signal for Channel 0.
K19
LJ_CLK_N
D, I
M3
COMP_H_CH0_P
D, I
M2
COMP_H_CH0_N
D, I
J4
COMP_H_CH1_P
D, I
J3
COMP_H_CH1_N
D, I
M18
COMP_H_CH2_P
D, I
M19
COMP_H_CH2_N
D, I
J17
COMP_H_CH3_P
D, I
J18
COMP_H_CH3_N
D, I
L3
COMP_L_CH0_P
D, I
L4
COMP_L_CH0_N
D, I
H1
COMP_L_CH1_P
D, I
J2
COMP_L_CH1_N
D, I
Noninverted DCL Low Comparator Signal for Channel 1. Differential signal is Logic 1 when the DUT output is higher than VOL. Inverted Low Comparator Signal for Channel 1.
L18
COMP_L_CH2_P
D, I
L17
COMP_L_CH2_N
D, I
Noninverted DCL Low Comparator Signal for Channel 2. Differential signal is Logic 1 when the DUT output is higher than VOL. Inverted Low Comparator Signal for Channel 2.
H20
COMP_L_CH3_P
D, I
J19
COMP_L_CH3_N
D, I
Noninverted DCL Low Comparator Signal for Channel 3. Differential signal is Logic 1 when the DUT output is higher than VOL. Inverted Low Comparator Signal for Channel 3.
M1
COMP_L_CH0_T
A, I, O
Center Tap. Center tap of two 50 resistor terminations for the low comparator differential inputs of Channel 0.
Rev. 0 | Page 9 of 36
ADATE207
Pin No. H2 Mnemonic COMP_L_CH1_T Input/Output 1 A, I, O Type Analog Description Center Tap. Center tap of two 50 resistor terminations for the low comparator differential inputs of Channel 1. Center Tap. Center tap of two 50 resistor terminations for the low comparator differential Inputs of Channel 2. Center Tap. Center tap of two 50 resistor terminations for the low comparator differential inputs of Channel 3. Center Tap. Center tap of two 50 resistor terminations for the high comparator differential inputs of Channel 0. Center Tap. Center tap of two 50 resistor terminations for the high comparator differential inputs of Channel 1. Center Tap. Center tap of two 50 resistor terminations for the high comparator differential inputs of Channel 2. Center Tap. Center tap of two 50 resistor terminations for the high comparator differential inputs of Channel 3. Bidirectional Multiplexed Address/Data Bus for CSR Register Access. Clocked by MCLK. Address Strobe for the Address/Data Bus. Clocked by MCLK. Read/Write Bar Signal for the Address Data Bus. High for reads. Clocked by MCLK. Mode Pin for Clock Generation. Tie to Logic low for normal operation. Positive Portion of the Master Clock Signal. Negative Portion of the Master Clock Signal. Reset Bar. Active low power-on reset signal. Scan Chain Data In. Tie to Logic high for normal operation. Scan Chain Data Out. Scan Chain Clock. Tie to Logic high for normal operation. Scan Chain Mode. Tie to Logic high for normal operation. Active Low Scan Chain Reset. Tie to Logic low for normal operation. Controls the output current of the differential open drain outputs. Thermal Sensing Diode Anode. Force current and measure voltage to measure die temperature stability. Must be connected to VSS. No Connect. Must be left unconnected. Connect to VSS. Power, 0.0 V. Power, 2.5 V. Power, 2.5 V. Power, 0.0 V
M20
COMP_L_CH2_T
A, I, O
Analog
H19
COMP_L_CH3_T
A, I, O
Analog
M4
COMP_H_CH0_T
A, I, O
Analog
H3
COMP_H_CH1_T
A, I, O
Analog
M17
COMP_H_CH2_T
A, I, O
Analog
H18
COMP_H_CH3_T
A, I, O
Analog
W15, V15, Y16, W16, Y17, W17, U16, V17, U18, T17, U19, U20, T19, T20, R18, R19 U13 V14 Y15 L1 K2 R4 D19 C8 A7 D18 E17 R1 P3
CS_AD[15:0]
I, O
LVCMOS25
CS_AS CS_RW_B CLKGEN_MD_EN MCLK_P MCLK_N RESET_B TDI TDO TCK TMS TRST_B REF_1K T_DIODE
I I I D, I D, I I I O I I I A, I, O A, I, O
LVCMOS25 LVCMOS25 LVCMOS25 LVCMOS25 LVCMOS25 LVCMOS25 LVCMOS25 LVCMOS25 LVCMOS25 LVCMOS25 LVCMOS25 Analog Analog
T2 F2, F1, F19, F20, T1, R3, R2, R20, N4, N17, P18 R17, U15, D9, D11, D12, D13, U10, U9, V7, V5 U8, U6, T18, V16 C9, C11, C13, C15, V11, V9 A3 to A1
TESTMODE NC SHIELD IOVSS IOVDD IOVDD VSS
I
LVCMOS25
A, I, O, P P P P P
GND GND VDD
Rev. 0 | Page 10 of 36
ADATE207
Pin No. Y20 to Y18, Y12, Y11, Y8, Y3 to Y1, W20, W1, V20, V1, N20, N1, K20, K1, J20, J1, C20, C1, B20, B1, A20 to A18, A13, A10, A9 W19, W18, W3, W2, V19, V18, V3, V2, U17, U14, U11, U7, U4, P17, P4, K17, K4, G17, G4, D17, D14, D10, D7, D4, C19, C18, C3, C2, B19, B18, B3, B2
1
Mnemonic VSS
Input/Output 1 P
Type GND
Description Power, 0.0 V.
VDD
P
VDD
Power, 2.5 V.
A = analog, D = differential, I = input, O = output, P = power.
Rev. 0 | Page 11 of 36
ADATE207 THEORY OF OPERATION
WAVEFORM MEMORY
Pattern data is used to address the waveform memory and is eight bits wide per channel, supporting 256 unique waveforms. The data width of the waveform memory is 26 bits wide per event or 104 bits wide per pin. The waveform memory data bits are partitioned into two fields, a 22-bit wide delay field, and a 4-bit event code field. The waveform memory is dual port allowing CPU access during pattern bursting. Pattern data is used as a pointer to one of the defined 256 waveforms, and can be partitioned into vector data and a time set pointer. Using three bits of vector data for the pin state, the other five bits can be used as 32 possible time sets. Supporting dual I/O per cycle, two sets of 3-bit vector data can be used in combination with two bits of a time set pointer providing four possible time sets. A straightforward trade off in time sets vs. device vectors per tester cycle is possible. Pattern data is qualified with the input signal PAT_DATA_VALID. When asserted, the pattern data is evaluated. When not asserted, events and timing edges are disabled and the input pattern data is ignored. Table 8. STIL-Compatible Events
Code N 0 1 Z U D P L H X T V l h t v Action No action Drive low Drive high Force off Force up Force down Force prior Compare low Compare high Compare unknown Compare off Compare valid Compare low window Compare high window Compare off window Compare valid window Description Default. Sets driver to low state. Sets driver to high state. Disables the driver and enable the load. Force Logic high. Enables the driver and disables the load. Force Logic low. Enables the driver and disables the load. Enable the driver. Edge compare low. Edge compare high. Don't care. Can be used to close window compare. Edge compare midband. Edge compare valid logic level. Start window compare against Logic low. Start window compare against Logic high. Start window compare against midband. Start window compare for valid logic level.
EVENT GENERATORS
Each channel has four programmable event generators. Each event generator inputs a delay, an event code from the waveform memory, and an 8-bit INPUT_DELAY. The waveform delay and the 8-bit INPUT_DELAY combine to produce programmable delays from T0 cycle starts. Each programmable delay can span up to 4 T0 periods and up to 163 s with a nominal delay resolution of 39.06 ps. There are 16 possible events. These events are compatible with STIL waveform events, as shown in Table 8, to create all of the conventional drive and compare formats. There is a programmable pipeline delay with 2.5 ns resolution between the drive events and the compare events allowing for round trip delay (RTD) compensation.
The delay generator uses a value expressed as the binary value bbbbbbbbbbbbbbbb.vvvvvv where there are 16 bits (b) left of the binary point and 6 bits (v) right of the binary point. The b bits represent an integer number of counts of 2.5 ns and the v bits represent a fractional value of 2.5 ns with a resolution of 2.5 ns/64 or 39.06 ps.
VERNIER RESOLUTION
The analog vernier delays are implemented using a modulo 60 algorithm and dividing 2.5 ns into 60 even parts. Because the delays are expressed using a binary representation, an internal mapping algorithm generates the delays. Ignoring analog timing errors, the actual delay produced for the six bits of vernier value (vvvvvv) is expressed as Delay = (2.5 ns/60) x INT (.5 + (vvvvvv x 60/64)) This mapping results in an inherent discontinuity in the linearity curve. Figure 7 shows the linearity of a typical vernier. On certain delay codes, the vernier exhibits non-monotonicity. To obtain a monotonic delay curve, these code jumps should be ignored by the user.
DELAY GENERATION
Each of the four events per channel has an independent delay generator (D0, D1, D2, and D3). Each delay generator triggers from a period start using either T0 or C0 periods. A delay value is the sum of three values: the user programmed delay that is programmed in waveform memory, a calibration delay indexed by the selected event, and a global INPUT_DELAY signal that is used across all channels. These delays are summed and triggered from the selected period start. The delays are generated using counts of 2.5 ns plus a 6-bit analog vernier delay. The analog vernier delay is expressed as a binary fractional value of 2.5 ns.
Rev. 0 | Page 12 of 36
ADATE207
2.5
per pin with individual fail counters. Fail outputs are resynchronized to T0 and output for fail processing. Fails can be masked on a per edge basis and match mode is supported. Masking of failures prevents incrementing of the fail counter and the setting of the accumulated fail registers. It does not prevent the fail signals from reflecting the comparison state of the expect edge. Strobe comparison fails are associated with the timing edge that generates the strobe. A pair of timing edges can be used to create a window of time over which to check the DUT output levels. Timing Edge D0 and Timing Edge D1 form a window with D0 opening the window and D1 closing the window. Timing Edge D2 and Timing Edge D3 are similarly employed for window comparisons. Window comparison fails are associated with the timing edge that generates the window close strobe. Window failures only come out on D1 or D3 edges. Table 9 shows the relationship between the edges on which the fails are detected and the bit position on the PAT_FAIL pins. Table 9. Edge and Window Fail Bit Descriptions
Bit 3 2 1 0
1
2.0 TYPICAL VERNIER 1.5
(ns)
1.0
0.5
05557-016
0
0
10
20
30
40
50
60
70
DELAY CODE
Figure 7. Delay Curve of a Typical Vernier
DRIVE AND COMPARE LOGIC
The drive logic consists of two high speed differential reset/set flip flops controlling the drive data and drive enable signals. They are controlled from the four events per channel, enabled via decode of the event code. In addition, the flip flops can be controlled from an adjacent channel event in a multiplex mode. The four-channel device can be multiplexed such that there are either four pins with four events each, or two pins with eight events each. The compare logic supports dual level comparators for voltage comparisons against VOL and VOH levels. The comparator outputs are checked against four possible states, low (less than VOL), high (greater than VOH), off or midband (between VOL and VOH), and valid (either above VOH or below VOL). The high comparator inputs (COMP_H) are Logic 1 when the DUT output is greater than VOH. The low comparator inputs (COMP_L) are Logic 1 when the DUT output is greater than VOL. The compare logic supports both single edge and window comparisons and can support up to four comparisons per cycle using the four events. Each comparison can generate a fail, accumulating
Fail1 PAT_FAIL_x[3] PAT_FAIL_x[2] PAT_FAIL_x[1] PAT_FAIL_x[0]
Description Edge D3 Fail and Window D2/D3 Fail Edge D2 Fail Edge D1 Fail and Window D0/D1 Fail Edge D0 Fail
Fail Mask Bit PAT_MASK[3] PAT_MASK[2] PAT_MASK[1] PAT_MASK[0]
PAT_FAIL_x refers to Channel 0 to Channel 3.
PAT_MASK inputs mask failures across the channels for four possible edges. Asserting PAT_MASK[0] masks failures for Timing Edge D0. When failures are masked, the accumulated fail register is not asserted, and the fail counts are not incremented. The PAT_FAIL_x outputs remain asserted if the expected vector is not seen allowing for match mode applications.
Rev. 0 | Page 13 of 36
ADATE207
INPUT_DELAY M M DUT
4 PAT_PATDATA T0
4 M
11 C
1 T0 PIPELINE REGISTER MCLK PIPELINE REGISTER CLK400 PIPELINE REGISTER C
PROGRAMMABLE RTD DELAY [0:31] C
11 C
FIFO 2 C
RTD COMPENSATION
T0
M
C
1 T0
PROGRAMMABLE T0 DELAY [0:30] T0
3 T0
FAIL DUTDATA
05557-002
LEGEND
Figure 8. Pipeline Diagram
Dual comparator inputs of the even channels (0 and 2) are routed to the compare logic of adjacent channels to provide x2 multiplexing. In x2 multiplexing, Pin 0 and Pin 2 comparator inputs route to Pin 1 and Pin 3, respectively, providing up to eight compare events per cycle on the multiplexed channels.
PAT_PATDATA_x[7:0] PAT_DATA_VALID PAT_MASK[3:0] INPUT_DELAY[7:0] PER_EARLY_T0EN PER_EARLY_C0EN
D
Q
CE
For proper functionality, drive actions, compare events, and fail accumulation mask requirements need to be coordinated within the device by adjusting the internal delay paths. The ADATE207 provides two programmable delay paths, the RTD pipeline and the T0 alignment pipeline, as shown in Figure 8. The pattern input and output signals are synchronous with the MCLK and pipelined on T0 periods. Figure 8 shows the pipeline diagram of the ADATE207. The T0 delay pipeline is programmable. It must be sufficiently deep to cover the round trip delay compensation, yet no deeper than the FIFO depth of the fail logic. The minimum T0 alignment pipeline depth needed is dependent on the programmed RTD compensation. The programmed T0 alignment pipeline depth must conform to the values listed in Table 10. The maximum number of 30 can be used in any circumstance. Depending upon the MCLK rate and the programmed RTD compensation, a smaller pipeline depth can be used. Table 10. T0 Pipeline Requirements
Minimum 10.5 + RTD/4 T0 Alignment Pipelines Maximum 30
MCLK
Figure 9. PER_EARLY_T0EN Pipelining
Figure 9 shows the pipelining of PER_EARLY_T0EN (the period start signal). It is pipelined with MCLK to control the T0 pipelines within the chip. It uses two MCLK pipelines within the chip to distribute the PER_EARLY_T0EN signal to all of the T0 pipeline registers. PER_EARLY_T0EN and PER_EARLY_C0EN, the period start signals, and the global INPUT_DELAY signals are pipelined into the ADATE207 with different depths. The PER_EARLY_T0EN and PER_EARLY_C0EN are pipelined with two MCLK pipelines prior to the enable pins of the T0 clocked pipelines. The INPUT_DELAY signals are not pipelined on T0 clock pipelines, but have only two MCLK pipelines prior to use by the timing generators. Figure 10 shows the relative pipelines for INPUT_DELAY and the period enables.
Rev. 0 | Page 14 of 36
05557-020
PIPELINE CONSIDERATIONS
T0 PIPELINE
ADATE207
comparator outputs of the digital pins to the time measurement unit signals, TMU_ARM, TMU_START, and TMU_STOP. Offchip control logic must select the appropriate TMU bus output signal from the ADATE207 and direct its selection to the TMU. The TMU outputs are high speed, differential 8 mA drivers and can be tristated for bus applications.
D PER_EARLY_T0EN PER_EARLY_C0EN M MCLK M CE T0 PIPELINE
Q
TIMING GENERATOR
INPUT DELAY[7:0]
05557-004
LOW JITTER CLOCK DRIVER
M M
Figure 10. INPUT_DELAY Pipeline
Figure 11 shows the timing of PER_EARLY_T0EN and the associated period delay offset, INPUT_DELAY. The INPUT_DELAY signal is added to each programmed delay across all channels. This input delay can change for each PER_EARLY_T0EN period. The delay from the pattern inputs to the DUT is four T0 pipeline delays, plus four MCLK pipeline delays, plus approximately 27.5 ns of analog delay, plus any programmed delay as shown in Figure 8. The delay from the pattern inputs to the fail outputs is eight PER_EARLY_T0EN periods plus the programmed T0 alignment pipeline depth.
The ADATE207 has 2-to-1 multiplexers in the DR_DATA_CH3 and DR_DATA_CH2 output drivers to allow an external low jitter clock signal to drive the DCL. This feature is not available on the DR_DATA_CH0 and DR_DATA_CH1 outputs.
CLOCK GENERATOR MODE
The ADATE207 incorporates a clock generation mode to allow it to be used as a programmable clock generator. In this mode, it is possible for each of the four channels to produce an independently programmable clock. To activate this mode, PER_EARLY_T0EN and the CLKGEN_MD_EN input need to be set high. In this mode, PAT_DATA_VALID has no effect. The pattern data signals (PAT_PATDATA_x) are interpreted as period offsets and the PAT_MASK[x] inputs are used as period start enables. See Table 11 for details of signal mapping. The use model for this mode is * Program drive high/drive low operations at Address 0 in the waveform memory. Depending on the delays, the value per edge, the duty cycle, and the start level can be adjusted per channel Four different clocks can be controlled by using PAT_MASK[N] as equivalent period start signals for an individual Channel N. Skew/insertion delay of the clocks can be adjusted individually by using I_PAT_PATADATA_N as an INPUT_DELAY signal for Channel N.
DUT CAPTURE
Each compare event can strobe the state of the dual comparators signals for each pin. These are resynchronized to T0 periods and output for use in mixed signal capture applications. There are four DUT capture pins per channel, PAT_DUTDATA_x and each can be configured to output the high or low comparators of each of the four possible compare events.
*
TMU MULTIPLEXER
The ADATE207 supports time measurement via an external time measurement unit (TMU) in the following configurations: * * Connect the high comparator output of any pin to TMU_ARM, TMU_START, or TMU_STOP. Connect the low comparator output of any pin to TMU_ARM, TMU_START, or TMU_STOP.
*
DEVICE RESET
The ADATE207 has an internal PLL and FIFO that require reset upon power up and changes to the MCLK input. The device has three reset controls. * * * RESET_B input pin for hard resets. CPU writeable control bit (Bit 00 in Register 0x19) for soft resets. CPU writeable control bit (Bit 03 in Register 0x19) to reset errors and internal FIFOs.
The time measurement unit select logic provides time and frequency measurement capability from the high or low comparator outputs of any digital pin. To accomplish this task, independent multiplexers direct the high and low
MCLK PER_EARLY_T0EN
05557-005
INPUT_DELAY[7:0] DELAY DELAY DELAY
Figure 11. Timing Diagram for PER_EARLY_T0EN and INPUT_DELAY
Rev. 0 | Page 15 of 36
ADATE207
After the power and MCLK inputs are stable, the device must be reset using the hard reset and error reset bits. The soft reset can be used to initialize registers at any time and does not reset the PLL or FIFOs. There are six rules of reset. Rule 1--on power up, keep the hard reset pin (RESET_B) asserted. Rule 2--if MCLK is unstable, keep the hard reset pin (RESET_B) asserted. Rule 3--after MCLK is stable, keep the hard reset pin (RESET_B) asserted for at least 20 s. Rule 4--after the 20 s of Rule 3 has elapsed, assert the error reset bit (Bit 03 in Register 0x19). Rule 5--the hard reset signal (RESET_B) can be asserted asynchronously to MCLK, but upon deassertion, must make setup and hold requirements upon the MCLK. Rule 6--the minimum pulse width of RESET_B must be at least three MCLK periods.
Table 11. Comparison Between Normal Mode and Clock Generation Mode
Period Start Waveform Memory Selection Input Delay Normal Mode (CLKGEN_MD_EN=0) A single signal for all four channels, I_PER_EARLY_T0EN. Each channel N is selected via the I_PAT_PATDATA_N vector every rising edge of I_MCLK. A single vector adjust input delay for all channels, INPUT_DELAY. Edge N for all channels can mask the fail operation every rising edge of I_MCLK via PAT_MASK[N]. Clock Generator Mode(CLKGEN_MD_EN=1) Four signals, one per channel; PAT_MASK[N] operates as a period start signal for channel N. Waveform memory location is fixed at Address 0. Four vectors are available, one per channel. For each Channel N, PAT_PATDATA_N operates as INPUT_DELAY for Channel N. No masking of fail operations is available.
Fail Masking
Rev. 0 | Page 16 of 36
ADATE207
TEMPERATURE DIODE
100A
COMP_CH0_P 50 COMP_CH0_T 50
05557-006
TDIODE TEMPERATURE DIODE FORCE I, MEASURE V
COMP_CH0_N DIFFERENTIAL LVPECL INPUT
Figure 14. Differential Input with Termination Resistors
EXTERNAL TERMINATION REQUIRED
ADATE207
05557-017
ADATE207
VOP VON ESD ESD
50 50
Figure 12. Block Diagram of Temperature Diode
740 720 700
POTENTIAL (mV)
680 660 640 620 600
05557-019
8mA
Figure 15. Differential Open Drain Output
0
20
40
60
80
100
120
TEMPERATURE (C)
The driver outputs are differential open-drain outputs. The outputs require termination through an external resistor to a positive supply and can be configured to be compatible with most PECL, and CML inputs. Their output currents can be programmed with a bias resistor to ground on the REF_1K pin. If the REF_1K pin is left open (>100 k) then the drive current is a nominal 8 mA. If a resistor is tied from REF_1K to ground, then the drive current is adjustable with the resistance value. A 1 k resistor yields a nominal 8 mA output current swing. Less resistance results in greater current. The relationship of drive current to resistance is given approximately by Drive_Current = 8 V/REXT Best practice suggests limiting the external resistance value between 800 and 2500 .
Figure 13. Characteristic of Temperature Diode
The block diagram of the temperature diode is shown in Figure 12, and its Output Voltage VS temperature characteristic is shown in Figure 13. Note in Figure 12 that 100 A is forced into the diode.
HIGH SPEED DIFFERENTIAL DCL INTERFACE
The ADATE207 uses a differential interface for connections to the DCL. The comparator inputs have on-chip 50 resistors for termination, configured to support either 50 parallel termination or 100 differential termination. The comparator inputs are compatible with LVPECL, LVDS, and most CML outputs. For PECL termination, connect the termination pin to VCC - 2.0 V or to an appropriate resistor to ground. For LVDS termination, do not connect the termination pin. For CML termination, either do not connect the termination pin or connect the termination pin to an appropriate supply.
05557-018
Rev. 0 | Page 17 of 36
ADATE207 CONTROL AND STATUS REGISTER INTERFACE
The ADATE207 uses a general-purpose, 16-bit bidirectional, multiplexed address data bus for computer access of the control and status registers of the part. All bus activity is registered at the interface synchronous to the master clock (MCLK), which is also used by the part for delay timing. Operations the bus supports include random access reads and writes, as well as the ability to access blocks of registers in burst. A description of each register is contained in the Control and Status Registers section of this document. by one or more data cycles. The quantity of data cycles is dependent on the activity on the CS_AD and CS_RW_B lines, which determine the type of operation to perform. The 16-bit address provided in the first cycle is comprised of two 5-bit address fields and an additional control field of 6-bits as shown in Table 12. The control field extends the associated 5-bit register address in use by steering the address and data to one or more banks of registers within the part. Register address space consists of five identifiable banks or groups of register implementations. These include one set of registers for each of the four channels and a fifth or common register space. Five bits of addressing are available to all five address spaces. The bank of registers for each channel duplicates the other in function and address, allowing a single write operation to be steered to multiple channels for simultaneous programming. The fifth bank of registers provides shared functions, common to all four channels, whose address range is mapped outside of the register address space used by the individual channel functions. All single register, random access operations are performed with the burst bit of the control field disabled. For these types of transactions, the 5-bit stop address field is ignored, and the 5-bit start address field is used as the register address of the operation.
READ/WRITE FUNCTION
The control and status register (CSR) bus interface supports the following functionalities: * The ability to enable groups of channels for write operations, allowing simultaneous programming across all the designated channels. The ability to select any single channel, or group of channels, to poll (read) status (where the return value is the bitwise logical OR of the status returned from each of the designated channels). The ability to read or write in a single burst operation to a sequential block of registers significantly reducing the time required to program the internal memories.
*
*
In multiplexing the address and data on the bus, each operation takes at least two cycles to complete. In all cases, read or write, the first cycle provides the 16-bit address. This cycle is followed Table 12. Address Bus Decoding
Address Bits Bit 15
Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bits[09:05] Bits[04: 00]
Description Burst Enable. 1 = initiate burst mode operation. 0 = enable normal read or write transactions. Common Enable. When set to 1, enables reads or writes to the common registers. This enable is valid in either normal or burst modes. Channel 3 Enable. When set to 1, enables reads or writes to Channel 3. This enable is valid in either normal or burst modes. Channel 2 Enable. When set to 1, enables reads or writes to Channel 2. This enable is valid in either normal or burst modes. Channel 1 Enable. When set to 1, enables reads or writes to Channel 1. This enable is valid in either normal or burst modes. Channel 0 Enable. When set to 1, enables reads or writes to Channel 0. This enable is valid in either normal or burst modes. Burst Stop Address. Used to set the last CSR address to read to, or write from, before looping back to the burst start address. This address is only valid when burst enable is set to 1. CSR Address (Burst Enable = 0). Used to set the CSR address for reading or writing. Burst Start Address (Burst Enable = 1). Used to set the first CSR address to read to, or write from, when bursting data. Burst writes or reads incrementally access successive registers up to, and including, the burst stop address.
Rev. 0 | Page 18 of 36
ADATE207
MCLK CYCLES ASSERTED FOR 2 OR MORE CYCLES WILL ALLOW 1 EXTRA CYCLE OF READ DATA HOLD ON BUS (OPTIONAL)
CS_AS
CS_RW_B
CS_AD
A1
WD1
A2
WD2
A3
RD3
A4
WD4
05557-010
1 CYCLE OF BUS TURN-AROUND + 8 CYCLES OF READ DATA DELAY
1 CYCLE OF BUS TURN-AROUND
Figure 16. Bus Interface Function Timing Diagram
Figure 16 shows the bus functional timing while performing both read and write operations. Highlights include * * The bus implements a synchronous protocol, where read and write transactions are slotted into MCLK cycles. The CS_AD bus lines, 2.5 V CMOS signals, can be tristated. To implement a multidrop bus, strict adherence to proper bus turnaround from reads to writes (and vice versa) is required. The initial bus turn around time for a read operation is indicative of the internal path length inside the ADATE207. After accepting a read transaction, the ADATE207 waits one MCLK cycle for bus turnaround, and then turns on its bus drivers to precharge the bus. There must be at least one MCLK cycle between a read followed by a write transaction, and between the address and read data cycles due to bus turnaround. The ADATE207 tristates the bus on the MCLK after it has finished driving the read data. A write transaction can be followed immediately by a read transaction. Likewise, a series of write transactions can be grouped together with no dead time in between transactions. To ease board timing, holding the CS_RW_B signal high allows the read data to stay on the bus one extra MCLK cycle. One application allows two clock cycles for read data to propagate to its destination. Note that holding CS_RW_B high for more that two cycles has no effect.
ADATE207. Note that the read data takes more than one clock cycle. The bus interface state machine controls the output enable accordingly. The write data is reregistered (retimed) to require only one MCLK cycle to write the data into the targeted register (or registers, in the case where multiple channels are selected).
Burst Mode
Burst mode is a special mode that allows for successive reads or writes with a predetermined addressing scheme. Figure 17 shows the burst mode operation of the bus. The primary purpose of burst mode is to allow fast writes into the waveform memory for each channel. Burst mode is initiated and completely controlled via the bus interface pins of the ADATE207. Burst mode is initiated with a special address cycle, as defined in Table 12. Burst mode cycles are shown in Figure 17 through Figure 19 and incorporate the following conditions: * The completion of burst mode is controlled by the address strobe signal. If address strobe is deasserted in a particular MCLK cycle, that becomes the last cycle of the burst. Only a series of burst writes or reads can occur. There can be no mixing of reads and writes in a burst sequence. The bus interface state machine takes over the internal register address only and the read/write selection signal. The CSR blocks and channel-specific memory accesses operate the same in burst mode as they do in the normal read/write transactions. There must be at least two MCLK cycles between a read burst followed by another read or write transaction, and between the address and read data cycles due to bus turnaround. The ADATE207 tristates the bus on the MCLK after it is finished driving read data, as shown in Figure 18. When extended read data hold mode is selected during a read burst, the internal address bus increments every other cycle, causing read data on the CS_AD bus to change every other cycle, as shown in Figure 19.
*
*
*
*
* * *
*
All external bus signals come into the ADATE207 and are registered by the MCLK. Then, the registered signals are used to interface to the four channel-specific register banks and the common block. Each register bank receives an address, data, the read/write signal, and a block select. Even though some portions of the internal timing circuitry run at a high rate than the master clock, all of the register blocks run at the master clock, MCLK, rate. When a block is selected, a read or write operation is performed. For read operations, data is enabled onto the read data bus of a block, and that data is OR'ed with four other block-specific RDATA busses to form the read data that is sent from the
*
*
Rev. 0 | Page 19 of 36
ADATE207
MCLK CYCLES
CS_AS
CS_AS LOW ENDS BURST
CS_RW_B
BURST ADDRESS CYCLE INITIATES BURST
Figure 17. Write Burst Mode Functional Timing
MCLK CYCLES
CS_AS
CS_AS LOW ENDS BURST
CS_RW_B CS_AD BA 1 CYCLE OF BUS TURN-AROUND + 8 CYCLES OF READ DATA DELAY RD1 RD2 RD3 RD4 RD5 RD6 RD7 RD8 1 CYCLE OF BUS TURN-AROUND A4 WD4
05557-012
Figure 18. Read Burst Mode Functional Timing
MCLK CYCLES
CS_AS
CS_AS LOW ENDS BURST EXTRA CYCLE ASSERTED CAUSES 2 CYCLES OF READ DATA HOLD TIME
CS_RW_B CS_AD BA
RD1 1 CYCLE OF BUS TURN-AROUND + 8 CYCLES OF READ DATA DELAY
RD2
RD3
RD4
A4
05557-011
CS_AD
BA
WD1 WD2 WD3 WD4 WD5 WD6 WD7 WD8
RA
RD
WD4
05557-013
1 CYCLE OF BUS TURN-AROUND
Figure 19. Read Burst Mode with Read Data Hold Functional Timing
Rev. 0 | Page 20 of 36
ADATE207 CONTROL AND STATUS REGISTERS
This section details the breakdown of the configuration and status registers in the ADATE207. An address map provides the locations of all registers, and the detailed descriptions that follow show how each register is used. Table 13. Address Map
Chip Address 0x00 0x01 0x02 0x03 0x04 0x05 0x06 0x07 0x08 0x09 0x0A 0x0B 0x0C 0x0D 0x0E 0x0F 0x10 0x11 0x12 0x13 to 0x18 0x19 1x1A 0x1B 0x1C 0x1D 0x1E 0x1F Register Description Comparator and Fail Status. Channel-specific address space. Fail Counter Low. Fail Counter High. Static Configuration. Dynamic Configuration. Waveform/Calibration Memory Address. Waveform D0 Vernier Delay and Action. Waveform D0 Course Delay. Waveform D1 Vernier Delay and Action. Waveform D1 Course Delay. Waveform D2 Vernier Delay and Action. Waveform D2 Course Delay. Waveform D3 Vernier Delay and Action. Waveform D3 Course Delay. Calibration Memory D0. Calibration Memory D1. Calibration Memory D2. Calibration Memory D3. DUT Data Selection. Unused. Reserved. Software Resets. Common register address space. Round Trip Delay Value. T0 Alignment Pipeline Depth. TMU Channel Select. Channel Multiplex Enable. Channel Status. Chip Information.
Rev. 0 | Page 21 of 36
ADATE207
CHANNEL SPECIFIC AND COMMON REGISTERS
Detailed register descriptions divided into channel-specific and common registers.
Channel Specific Registers
Name: Address: Type: Comparator and Fail Status 0x00 Read
Table 14. Comparator and Fail Status
Position Bits[15:08] Bit 07 Bit 06 Description Not used. Edge Error: Edges Longer Than 4 T0 Cycles. This occurs when the edge delay counters are reloaded before they complete counting down, thus, causing a missing edge. Edge Error: Out of Order Edge Strobes. This occurs when one or more edge delay counters complete counting out of order (wrong action code is paired with an edge), or two edge delay counters complete counting at the same CLK400 edge (causing a missing edge). Edge Error: Adder Overflow. This occurs when the residue or calibration constant adders overflow causing edge delays to wrap around. This results in incorrect edge timing. Edge Error: Two Edges Too Close. This occurs when either the drive or compare verniers receive nonincreasing delay values in back-to-back CLK400 cycles. The verniers become unsynchronized and cause incorrect edge timing thereafter. Accumulated Fail Registers. These four data bits provide up to four possible DUT failures--one for each edge delay. The bits are decoded as follows: Bit 00 = D0 edge or window failures. Bit 01 = D1 edge failure or D0/D1 window failures. Bit 02 = D2 edge or window failures. Bit 03 = D3 edge failure or a D3/D2 window failure. Reset State 0x00 0x0 0x0
Bit 05 Bit 04
0x0 0x0
Bits[03:00]
0x0
Name: Address: Type:
Fail Counter Low 0x01 Read/Write
Table 15. Fail Counter Low
Position Bits[15:00] Description Fail Counter Data Low Order Bits. This field contains the 16 LSBs of the fail counter. This register and the fail counter data high register represent a binary encoded, 32-bit, number of fail events (up to 4 fail events per T0 period) detected during the last pattern burst. The CPU reads this register while the pattern is bursting, capturing a snapshot of the fail count at the time of reading the low register. Writes during pattern burst can produce indeterminate results if fails are occurring during the write cycle. The CPU must read the contents of the counter by performing sequential reads from the fail counter low register followed by a read from the fail counter high register. Reading from the fail counter low register performs the transfer of data from the counter to a temporary holding register. Reading from the fail counter high register reads solely from the temporary holding register. For diagnostics, the CPU can preload the contents of the counter by performing sequential writes to the Fail Counter CHx data low register followed by a write to the Fail Counter Chx data high register. Writing to the Fail Counter Chx data high register performs the transfer of data from temporary holding registers to the 32-bit counter. Reset State 0x0000
Rev. 0 | Page 22 of 36
ADATE207
Name: Address: Type: Fail Counter High 0x02 Read/Write
Table 16. Fail Counter High
Position Bits[15:00] Description Fail Counter Data High. This field contains the 16 MSBs of the fail counter. See Table 15, the fail counter low register, for more information. Reset State 0x0000
Name: Address: Type:
Static Configuration 0x03 Read/Write
Table 17. Static Configuration
Position Bits[15:04] Bit 03 Description Not Used. Ch_Data_Low. A high with edges disabled produces a low level output from the drive data (DR_DATA) signal regardless of pattern data. Pulsing this bit allows the data to be preset to a low level output prior to bursting a pattern. Control of the drive data is pattern data dependent when a pattern is burst. If both Data_High and Data_Low are high, the data is indeterminate. Ch_Data_High. A high with edges disabled produces a high level output from the drive data (DR_DATA) signal regardless of pattern data Pulsing this bit allows the data to be preset to a high level output prior to bursting a pattern. Control of the drive data is pattern data dependent when a pattern is burst. Ch_Driver_Off. A high with edges disabled produces a low level output from the drive enable (DR_EN) signal, tristating the driver regardless of pattern data. Pulsing this bit allows the driver to tristate prior to bursting a pattern. Control of the driver is pattern data dependent when a pattern is burst. If both Driver_On and Driver_Off are high, the drive enable signal (DR_EN) is indeterminate. Ch_Driver_On. A high with edges disabled produces high level output from the drive enable (DR_EN) signal, enabling the driver regardless of pattern data. Pulsing this bit enables the driver prior to bursting a pattern. Control of the driver is pattern data dependent when a pattern is burst. Reset State 0x000 0
Bit 02
0
Bit 01
0
Bit 00
0
Rev. 0 | Page 23 of 36
ADATE207
Name: Address: Type: Dynamic Configuration 0x04 Read/Write
Table 18. Dynamic Configuration
Position Bits[15:05] Bit 04 Description Not Used. Edge Generation Enable. Low turns off the channel's edge delay generators. High turns on the channel's edge delay generators. T0 and C0 Select. Low selects T0 as the pattern cycle clock for the edge delay generators. High selects C0 as the pattern cycle clock for the edge delay generators. When in C0 mode, compare events are illegal and treated as no action. Fail Mask. High statically disables channel failures by the Accumulated Fail registers and the fail counter. Low allows use of the pattern fail mask signals. Low Jitter Clock Enable. High statically enables the low jitter clock input onto the channel's drive data output. Low disables the low jitter clock for the channel. This feature only applies to Channel 2 and Channel 3. The low jitter clock signal is not available on Channel 0 and Channel 1. Fail Counter Increment. Writing a 1 to this bit creates a pulse to increment the fail counter. Writing a 0 has no effect. Reset State 0x000
Bit 03
0
Bit 02
0
Bit 01
0
Bit 00
0
Waveform and Calibration Memory Addresses
To gain access to the timing set memory, the timing set memory address must be programmed to the desired address. Name: Address: Type: Waveform/Calibration Memory Address 0x05 Read/Write
Table 19. Waveform/Calibration Memory Address
Position Bits[15:10] Bits[09:08] Description Not Used. Waveform Memory Address Auto-Increment. Sets the address to auto-increment on a read from, or write to, the following registers, based on the value programmed into this field: 0 = Waveform D0 Course Delay or Calibration Memory D0. 1 = Waveform D1 Course Delay or Calibration Memory D1. 2 = Waveform D2 Course Delay or Calibration Memory D2. 3 = Waveform D3 Course Delay or Calibration Memory D3. Waveform Memory Programming Address. Sets the address into either the waveform memory or calibration memory. Writing to, or reading from, the Waveform Dx course delay, Waveform Dx vernier delay and action, or calibration memory data registers uses the address value programmed into this register. Reads of this register reflect the current state of the auto-incremented address. Reset State 0x00 0
Bits[07:00]
0
Rev. 0 | Page 24 of 36
ADATE207
Name: Address: Type: Waveform D0 Vernier Delay and Action 0x06 Read/Write
Table 20. Waveform D0 Vernier Delay and Action
Position Bits[15:10] Bits[09:04] Bits[03:00] Description D0 Vernier Delay. The vernier delay is represented in binary by the equation, vvvvvv x (2.5 ns/64). Not Used. D0 Action. A binary encoded data field. 0x0 = no action. 0x1 = drive low. 0x2 = drive high. 0x3 = force off. 0x4 = force on. 0x5 = force down. 0x6 = force up. 0x7 = edge compare low. 0x8 = edge compare high. 0x9 = edge compare off. 0xA = edge compare valid. 0xB = open window low. 0xC = open window high. 0xD = open window high-Z. 0xE = open window valid. 0xF = compare unknown. Reset State Undefined 0x00 Undefined
Name: Address: Type:
Waveform D0 Vernier Delay and Action 0x07 Read/Write
Table 21. Waveform D0 Course Delay
Position Bits[15:00] Description D0 Course Delay. Number of 2.5 ns clock periods to count. When this count is completed, the vernier delay (defined by the D0 vernier value programmed into the Waveform D0 vernier delay and action register) is added to the D0 course delay to place an edge in time. Waveform D0 vernier delay and action must be written immediately before this register for the waveform memory to be written correctly. Reset State Undefined
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ADATE207
Name: Address: Type: Waveform D1 Vernier Delay and Action 0x08 Read/Write
Table 22. Waveform D1 Vernier Delay and Action
Position Bits[15:10] Bits[09:04] Bits[03:00] Description D1 Vernier Delay. The vernier delay is represented in binary by the equation, vvvvvv x (2.5 ns/64). Not Used. D1 Action. A binary encoded data field. 0x0 = no action. 0x1 = drive low. 0x2 = drive high. 0x3 = force off. 0x4 = force on. 0x5 = force down. 0x6 = force up. 0x7 = edge compare low. 0x8 = edge compare high. 0x9 = edge compare off. 0xA = edge compare valid. 0xF = close window/compare unknown. Reset State Undefined 0x00 Undefined
Name: Address: Type:
Waveform D1Course Delay 0x09 Read/Write
Table 23. Waveform D1 Course Delay
Position Bits[15:00] Description D1 Course Delay. Number of 2.5 ns clock periods to count. When this count is completed, add the vernier delay (defined by the D1 vernier value programmed into the waveform D1 vernier delay and action register) to the D1 course delay to place an edge in time. Waveform D1 vernier delay and action must be written immediately before this register for the waveform memory to be correctly written. Reset State Undefined
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ADATE207
Name: Address: Type: Waveform D2 Vernier Delay and Action 0x0A Read/Write
Table 24. Waveform D2 Vernier Delay and Action
Position Bits[15:10] Bits[09:04] Bits[03:00] Description D2 Vernier Delay: The vernier delay is represented in binary by the equation, vvvvvv x (2.5 ns/64) Not Used. D2 Action. A binary encoded data field. 0x0 = no action. 0x1 = drive low. 0x2 = drive high. 0x3 = force off. 0x4 = force on. 0x5 = force down. 0x6 = force up. 0x7 = edge compare low. 0x8 = edge compare high. 0x9 = edge compare off. 0xA = edge compare valid. 0xB = open window low. 0xC = open window high. 0xD = open window high-Z. 0xE = open window valid. 0xF = compare unknown. Reset State Undefined 0x00 Undefined
Name: Address: Type:
Waveform D2 Course Delay 0x0B Read/Write
Table 25. Waveform D2 Course Delay
Position Bits[15:00] Description D2 Course Delay. Number of 2.5 ns clock periods to count. When this count is completed, the vernier delay (defined by the D2 vernier value programmed into the waveform D2 vernier delay and action register) is added to the D2 course delay to place an edge in time Waveform D2 vernier delay and action must be written immediately before this register for the waveform memory to be correctly written. Reset State Undefined
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ADATE207
Name: Address: Type: Waveform D3 Vernier Delay and Action 0x0C Read/Write
Table 26. Waveform D3 Vernier Delay and Action
Position Bits[5:10] Bits[09:04] Description D3 Vernier Delay: The vernier delay is represented in binary by the equation, vvvvvv x (2.5 ns/64) Not Used. D3 Action: A binary encoded data field. 0x0 = no action. 0x1 = drive low. 0x2 = drive high. 0x3 = force off. 0x4 = force on. 0x5 = force down. 0x6 = force up. 0x7 = edge compare low. 0x8 = edge compare high. 0x9 = edge compare off. 0xA = edge compare valid. 0xF = close window/compare unknown. Reset State Undefined
Bits[03:00]
Undefined
Name: Address: Type:
Waveform D3 Course Delay 0x0D Read/Write
Table 27. Waveform D3 Course Delay
Position Bits[15:00] Description D3 Course Delay. Number of 2.5 ns clock periods to count. When this count is completed, the vernier delay (defined by the D3 vernier value programmed into the waveform D3 vernier delay and action register) is added to the D3 course delay to place an edge in time. Waveform D3 vernier delay and action must be written immediately before this register for the waveform memory to be correctly written. Reset State Undefined
Name: Address: Type:
Calibration Memory D0 0x0E Read/Write
Table 28. Calibration Memory D0
Position Bits[15:08] Bits[07:00] Description Not Used. D0 Calibration Constant (CCCCCCCC). The calibration delay is represented in binary by the equation CCCCCCCC x (2.5 ns/64). Reset State 0x000 Undefined
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ADATE207
Name: Address: Type: Calibration Memory D1 0x0F Read/Write
Table 29. Calibration Memory D1
Position Bits[15:08] Bits[07:00] Description Not Used. D1 Calibration Constant (CCCCCCCC). The calibration delay is represented in binary by the equation CCCCCCCC x (2.5 ns/64) Reset State 0x000 Undefined
Name: Address: Type:
Calibration Memory D2 0x10 Read/Write
Table 30. Calibration Memory D2
Position Bits[15:08] Bits[07:00] Description Not Used. D2 Calibration Constant (CCCCCCCC). The calibration delay is represented in binary by the equation CCCCCCCC x (2.5 ns/64) Reset State 0x000 Undefined
Name: Address: Type:
Calibration Memory D2 0x11 Read/Write
Table 31. Calibration Memory D3
Position Bits[15:08] Bits[07:00] Description Not Used. D3 Calibration Constant (CCCCCCCC). The calibration delay is represented in binary by the equation CCCCCCCC x (2.5 ns/64). Reset State 0x000 Undefined
DUT Data Selection
Name: Address: Type: DUT Data Selection 0x12 Read/Write
Table 32. DUT Data Selection
Position Bit 15 Bits[14:12] Description Not Used. PAT_DUTDATA3 Select. A binary encoded data field that selects which edge and which comparator to drive out of the ADATE207 PAT_DUTDATAx[3] pin. 0x0 = Edge D0 low comparator. 0x1 = Edge D0 high comparator. 0x2 = Edge D1 low comparator. 0x3 = Edge D1 high comparator. 0x4 = Edge D2 low comparator. 0x5 = Edge D2 high comparator. 0x6 = Edge D3 low comparator. 0x7 = Edge D3 high comparator. Not Used.
Rev. 0 | Page 29 of 36
Reset State 0
0x00
Bit 11
0
ADATE207
Position Bits[10:08] Description PAT_DUTDATA2 Select. A binary encoded data field that selects which edge and which comparator to drive out of the ADATE207 PAT_DUTDATAx[2] pin. 0x0 = Edge D0 low comparator. 0x1 = Edge D0 high comparator. 0x2 = Edge D1 low comparator. 0x3 = Edge D1 high comparator. 0x4 = Edge D2 low comparator. 0x5 = Edge D2 high comparator. 0x6 = Edge D3 low comparator. 0x7 = Edge D3 high comparator. Not Used PAT_DUTDATA1 Select. A binary encoded data field that selects which edge and which comparator to drive out of the ADATE207 PAT_DUTDATAx[1] pin. 0x0 = Edge D0 low comparator. 0x1 = Edge D0 high comparator. 0x2 = Edge D1 low comparator. 0x3 = Edge D1 high comparator. 0x4 = Edge D2 low comparator. 0x5 = Edge D2 high comparator. 0x6 = Edge D3 low comparator. 0x7 = Edge D3 high comparator. Not Used PAT_DUTDATA0 Select. A binary encoded data field that selects which edge and which comparator to drive out of the ADATE207 PAT_DUTDATAx[0] pin. 0x0 = Edge D0 low comparator. 0x1 = Edge D0 high comparator. 0x2 = Edge D1 low comparator. 0x3 = Edge D1 high comparator. 0x4 = Edge D2 low comparator. 0x5 = Edge D2 high comparator. 0x6 = Edge D3 low comparator. 0x7 = Edge D3 high comparator. Reset State 0x0
Bit 07 Bits[06:04]
0 0x0
Bit 03 Bits[02:00]
0 0x0
CHIP-SPECIFIC (COMMON) REGISTERS
Name: Address: Type: Software Resets 0x19 Write
Table 33. Software Resets
Position Bit 15 Bits[14:04] Bit 03 Description DLL Ready. Indicates that the internal PLL and DLL are stable after a reset and/or MCLK change. Not Used. Error Registers Clear. Writing a 1 to this bit creates a pulse to clear all the delay generation errors for all channels and resets the edge generation logic. Writing a 0 has no affect. Accumulated Fail Registers Clear. Writing a 1 to this bit creates a pulse to clear the accumulated fail registers for all channels. Writing a 0 has no affect. Reset State Dynamic 0x000 0x0
Bit 02
0x0
Rev. 0 | Page 30 of 36
ADATE207
Position Bit 01 Description Fail Counters Clear. Writing a 1 to this bit creates a pulse to clear the fail counters for all channels. Writing a 0 has no affect. Soft Reset. Writing this register bit to a Logic 1 causes the ADATE207 to generate a software reset. This is logically equivalent to a hard reset via the I_RESET_B pin. All logic and registers are reset. Reset State 0x0
Bit 00
0x0
Name: Address: Type:
Round Trip Delay Value 0x1A Read/Write
Table 34. Round Trip Delay Value
Position Bits[15:05] Bits[4:00] Description Not Used. Round Trip Delay Value. Programs the round-trip delay from the ADATE207 drive to compare pins, in units of 2.5 ns. The maximum delay is 80 ns (value = 31) and the minimum delay is 2.5 ns (value = 0). Reset State 0x000 0x0
Name: Address: Type:
T0 Alignment Pipeline Depth 0x1B Read/Write
Table 35. T0 Alignment Pipeline Depth
Position Bits[15:05] Bits[04:00] Description Not Used. T0 Alignment Pipeline Depth. This pipeline value matches the edge generation delay for compare edges thereby correctly aligning compare fails and DUT data to the T0 pipeline. It should be programmed no higher than 30 and 10.5+ RTD/4. Reset State 0x000 0x0
TMU Channel Select
This register selects one of four channels to independently direct to the TMU arm, start, and stop buses. Name: Address: Type: TMU Channel Select 0x1C Read/Write
Table 36. TMU Channel Select
Position Bits[15:12] Bit 11 Bits[10:08] Description Not Used. TMU Stop Enable. A zero tristates the TMU stop output. TMU Stop, Channel Select Multiplexer. A binary encoded data field. 0x0 selects Channel 0 comparator high. 0x1 selects Channel 0 comparator low. 0x2 selects Channel 1 comparator high. 0x3 selects Channel 1 comparator low. 0x4 selects Channel 2 comparator high. 0x5 selects Channel 2 comparator low. 0x6 selects Channel 3 comparator high. 0x7 selects Channel 3 comparator low. TMU Start Enable. A zero tristates the TMU stop output. TMU Start, Channel Select Multiplexer. A binary encoded data field.
Rev. 0 | Page 31 of 36
Reset State 0x00 0 0x00
Bit 07 Bits[06:04]
0 0x00
ADATE207
Position Description 0x0 selects Channel 0 comparator high. 0x1 selects Channel 0 comparator low. 0x2 selects Channel 1 comparator high. 0x3 selects Channel 1 comparator low. 0x4 selects Channel 2 comparator high. 0x5 selects Channel 2 comparator low. 0x6 selects Channel 3 comparator high. 0x7 selects Channel 3 comparator low. TMU Arm Enable. A zero tristates the TMU Stop output. TMU Arm Channel Select Multiplexer. A binary encoded data field. 0x0 selects Channel 0 comparator high. 0x1 selects Channel 0 comparator low. 0x2 selects Channel 1 comparator high. 0x3 selects Channel 1 comparator low. 0x4 selects Channel 2 comparator high. 0x5 selects Channel 2 comparator low. 0x6 selects Channel 3 comparator high. 0x7 selects Channel 3 comparator low. Reset State
Bit 03 Bits[02:00]
0 0x00
Name: Address: Type:
Channel Multiplex Enable 0x1D Read/Write
Table 37. Channel Multiplex Enable
Position Bits[15:02] Bit 01 Bit 00 Description Not Used. CH2 Multiplex Enable. This channel can be 2-way multiplexed. Setting this bit to 1 enables Channel 3 to be multiplexed on Channel 2. CH0 Multiplex Enable. This channel can be 2-way multiplexed. Setting this bit to 1 enables Channel 1 to be multiplexed on Channel 0. Reset State 0x0000 0 0
Name: Address: Type:
Channel Status 0x1E Read
Table 38. Channel Status
Position Bit 15 Description Channel 3 Failure. This indicates that the channel had a failure. This signal is the Logic OR of the accumulated fail registers (AFRs) of the channel. More details of the fail can be found by reading the AFRs or fail counter for Channel 3. Channel 2 Failure. This indicates that the channel had a failure. This signal is the Logic OR of the accumulated fail registers (AFRs) of the channel. More details of the fail can be found by reading the AFRs or fail counter for Channel 2. Channel 1 Failure. This indicates that the channel had a failure. This signal is the Logic OR of the accumulated fail registers (AFRs) of the channel. More details of the fail can be found by reading the AFRs or fail counter for Channel 1. Channel 0 Failure. This indicates that the channel had a failure. This signal is the Logic OR of the accumulated fail registers (AFRs) of the channel. More details of the fail can be found by reading the AFRs or fail counter for Channel 0. Channel 3 Timing Error. This indicates that the channel had a timing error. This signal is the Logic OR of the timing error flags of the channel. More details of the error can be found by reading the error flags for Channel 3.
Rev. 0 | Page 32 of 36
Reset State 0x0
Bit 14
0x0
Bit 13
0x0
Bit 12
0x0
Bit 11
0x0
ADATE207
Position Bit 10 Description Channel 2 Timing Error. This indicates that the channel had a timing error. This signal is the Logic OR of the timing error flags of the channel. More details of the error can be found by reading the error flags for Channel 2. Channel 1 Timing Error. This indicates that the channel had a timing error. This signal is the Logic OR of the timing error flags of the channel. More details of the error can be found by reading the error flags for Channel 1. Channel 0 Timing Error. This indicates that the channel had a timing error. This signal is the Logic OR of the timing error flags of the channel. More details of the error can be found by reading the error flags for Channel 0. Channel 3 High Comparator Output. This indicates the state of the high comparator. When high, the DUT logic output is higher than the VOH. When low, the DUT output is lower than the VOH. Channel 3 Low Comparator Output. This indicates the state of the low comparator. When low, the DUT logic output is lower than the VOL. When high, the DUT output is higher than the VOL. Channel 2 High Comparator Output. This indicates the state of the high comparator. When high, the DUT logic output is higher than the VOH. When low, the DUT output is lower than the VOH. Channel 2 Low Comparator Output. This indicates the state of the low comparator. When low, the DUT logic output is lower than the VOL When high, the DUT output is higher than the VOL. Channel 1 High Comparator Output. This indicates the state of the high comparator. When high, the DUT logic output is higher than the VOH. When low, the DUT output is lower than the VOH. Channel 1 Low Comparator Output. This indicates the state of the low comparator. When low, the DUT logic output is lower than the VOL When high, the DUT output is higher than the VOL. Channel 0 High Comparator Output. This indicates the state of the high comparator. When high, the DUT logic output is higher than the VOH. When low, the DUT output is lower than the VOH. Channel 0 Low Comparator Output. This indicates the state of the low comparator. When low, the DUT logic output is lower than the VOL. When high, the DUT output is higher than the VOL. Reset State 0x0
Bit 09
0x0
Bit 08
0x0
Bit 07 Bit 06 Bit 05 Bit 04 Bit 03 Bit 02 Bit 01 Bit 00
Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined
Name: Address: Type:
Chip Information 0x1F Read
Table 39. Chip Information
Position Bits[15:00] Description Reserved. Reset State N/A
Rev. 0 | Page 33 of 36
ADATE207 APPLICATION INFORMATION
TIME MEASUREMENT SUPPORT
The ADATE207 contains support for time measurement through an external time measurement unit (TMU) in the following ways: * * * Connect the high comparator output of any channel to TMU arm, TMU start, or TMU stop. Connect the low comparator output of any channel to TMU arm, TMU start, or TMU stop. Tristate the TMU multiplexer outputs using an enable control bit. The time measurement unit select logic provides time and frequency measurement capability from any digital pin high or low comparator output. To accomplish this task, independent multiplexers are employed for directing the high or low comparator outputs of the digital pins to the (three) time measurement unit signals, TMU_ARM, TMU_START, and TMU_STOP. Off-chip control logic must select the appropriate TMU bus output signal from the ADATE207 devices on the board and direct its selection to the TMU.
Rev. 0 | Page 34 of 36
ADATE207 OUTLINE DIMENSIONS
27.00 BSC SQ A1 CORNER INDEX AREA
20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 A B C D E F G H J K L M N P R T U V W Y
BALL A1 INDICATOR 24.13 BSC SQ
TOP VIEW
BOTTOM VIEW
1.27 BSC
DETAIL A
1.70 MAX 0.10 MIN
DETAIL A
1.00 0.80 0.60 0.70 0.60 0.50
0.25 MIN (4x)
0.90 0.75 0.60 BALL DIAMETER
COPLANARITY 0.20 SEATING PLANE
COMPLIANT TO JEDEC STANDARDS MO-192-BAL-2
Figure 25. 256-Lead Ball Grid Array, Thermally Enhanced [BGA_ED] (BP-256) Dimensions shown in millimeters
ORDERING GUIDE
Model ADATE207BBP ADATE207BBPZ 2
1
2
Temperature Range 1 -25C to +85C -25C to +85C
Package Description 256-Lead Ball Grid Array, Thermally Enhanced [BGA_ED] 256-Lead Ball Grid Array, Thermally Enhanced [BGA_ED]
Package Option BP-256 BP-256
Guaranteed by design, not subject to production test. Z = RoHS Compliant Part.
Rev. 0 | Page 35 of 36
ADATE207 NOTES
(c)2007 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D05557-0-5/07(0)
Rev. 0 | Page 36 of 36

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